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30409hkim 20070523-s00003 no.a0858-1/24 ver.0.09 LC87F76C8A overview the LC87F76C8A is an 8-bit microcom puter that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hard ware features such as 1 28k-byte flash rom (onboard programmable), 4k-byte ram, an on-chip debugger, an lcd controller/driver, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or 8-bit pwms), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a day and time co unter, a synchronous sio interface (with automatic block transmission/reception capabilities), an as ynchronous/synchronous sio in terface, a uart interface (full duplex), a 8-bit 12-channel ad converter, two 12-bit pwm channels, a high-speed clock counter, a system clock frequency divider, a small signal detector, an infrared remote controller receiver function, and a 22-source 10-vector interrupt feature. features ? flash rom ? capable of on-board-programming with a wide range of souce voltages: 3.0 to 5.5v. ? block-erasable in 2-byte units ? 131072 8 bits (LC87F76C8A) ? ram ? 4096 9 bits (LC87F76C8A) ? minimum bus cycle time ? 83.3ns (12mhz) v dd =3.0 to 5.5v ? 125ns (8mhz) v dd =2.5 to 5.5v ? 250ns (4mhz) v dd =2.2 to 5.5v note: the bus cycle time here refers to the rom read speed. ordering number : ena0858 cmos ic from 128k byte, ram 4k byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F76C8A no.a0858-2/24 ? minimum instruction cycle time (tcyc) ? 250ns (12mhz) v dd =3.0 to 5.5v ? 375ns (8mhz) v dd =2.5 to 5.5v ? 750ns (4mhz) v dd =2.2 to 5.5v ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1-bit units 23 (p1n, p30 to p31, p70 to p73, p8n, xt2) ports whose i/o direction can be designated in 4-bit units 8 (p0n) ? normal withstand voltage input port 1 (xt1) ? lcd ports segment output 32 (s00 to s31) common output 4 (com0 to com3) bias terminals for lcd driver 3 (v1 to v3) other functions input/output ports 32 (pan, pbn, pcn, pdn,) input ports 7 (pln) ? dedicated oscillator ports 2 (cf1, cf2) ? reset pins 1 ( res ) ? power pins 6 (v ss 1 to v ss 3, v dd 1 to v dd 3) ? lcd controller 1) seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) 2) segment output and common output can be switched to general-purpose input/output ports ? small signal detection (mic signals etc) 1) counts pulses with the level whic h is greater than a preset value 2) 2-bit counter ? timers ? timer 0: 16-bit timer/counter with two capture registers. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmab le prescaler (with 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with 16-b it capture registers) mode 3: 16-bit counter (with 16-bit capture registers) ? timer 1: 16-bit timer that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer with an 8-bit pr escaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? day and time counter 1) used with a base timer, the day and time counter can be used as a 65000 day + mi nute + second counter.
LC87F76C8A no.a0858-3/24 ? high-speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). 2) can generate output real-time. ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8-data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8-data bits, stop detect) ? uart ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2-bit in continuous data transmission) ? built-in baudrate generator * when using uart, set p0lddr (poddr: bit0) to ?0? ? ad converter: 12 bits 12 channels ? pwm: multi frequency 12-bit pwm 2 channels ? infrared remote control receiver circuit 1) noise reduction function (time constant of noise reduction filter: approx. 120 s, when selecting a 32.768khz crystal oscillator as a reference clock.) 2) x ? tal hold mode cancellation function ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? clock output function 1) can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock. 2) can output the source oscillation clock for the sub clock.
LC87F76C8A no.a0858-4/24 ? interrupts ? 22 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interr upts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/remote control receiver 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/uart1 receive 8 0003bh h or l sio1/uart1 transmit 9 00043h h or l adc/mic/t6/t7/pwm4, pwm5 10 0004bh h or l port 0/t4/t5 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? iflg (list of interrupt source flag function) 1) shows a list of interrupt source flags that cau sed a branching to a particular vector address ? subroutine stack levels: 2048 levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock, with internal rf and external rd ? crystal oscillation circuit: for low-speed system clock, with internal rf and external rd ? multifrequency rc oscillation circuit (internal): for system clock 1) adjustable in 4% (typ) increments from the selected center frequency. 2) measures the frequency of the source oscillation cloc k using the input signal from xt1 as the reference. ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? system clock multiplier function ? allows the 2 or 3 times the clock frequency to be selected when the crystal oscillation output is used as the system clock.
LC87F76C8A no.a0858-5/24 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. (some parts of the serial transfer function stops operation.) 1) oscillation is not stopped automatically. 2) canceled by a system reset or occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, x?tal, and multifrequency rc oscillators automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, and int2, pins to the specified level (3) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer and infrared remote controller circuit. 1) the cf, rc, and multifrequency rc oscillators automatically stop operation 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, and int2 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit (5) having an interrupt source established in the infrared remote control receiver circuit ? on-chip debugger ? supports software debugging with the ic mounted on the target board. ? package form ? qip80(14 14): lead-free type ? tqfp80j(12 12): lead-free type ? development tools ? on-chip debugger: tcb87-typeb + LC87F76C8A ? flash rom programming board package programming boards qip80(14 14) w87f71256qf tqfp80j(12 12) w87f71256sq ? flash rom programmer maker model supported version (note) device flash support group, inc (single) af9708/af9709/af9709b (including models manufactured by ando electric co., ltd.) LC87F76C8A af9723 (main unit) (including models manufactured by ando electric co., ltd.) flash support group, inc (gang) af9833 (unit) (including models manufactured by ando electric co., ltd.) LC87F76C8A sanyo skk(sanyo fws) application version: after 1.04 chip data version: after 2.09 LC87F76C8A note: check for the latest version. ? same package and pin assignment as mask rom version. 1) lc877600 series options can be specified by using flash rom data. thus the board used for mass production can be used for debugging and evaluation without modifications. 2) if the program for the mask rom version is used, the size of the available rom/ra m spaces is the same as that of the mask rom version.
LC87F76C8A no.a0858-6/24 package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3255 3290 pin assignment *when using uart, set p0lddr (poddr: bit0) to ?0? sanyo: qfp80(14 14) ?lead-free type? sanyo: tqfp80j(12 12) ?lead-free type? v1/pl4/dbgp0 v2/pl5/dbgp1 v3/pl6/dbgp2 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/micin/an7 p70/int0/t0lcp/an8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v ss 2 v dd 2 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1 s0/pa0 p73/int3/t0in/rmin p72/int2/t0in/nkin p71/int1/t0hcp/an9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30/ pwm4 v ss 3 v dd 3 p31/ pwm5 p00/utx1* p01/urx1* p02 p03 p04 p05/cko p06/t6o p07/t7o p10/so0 p11/si0/sb0 p12/sck0 p13/so1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LC87F76C8A top view sanyo : qfp80(14x14) 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.25 0.65 (0.83) (2.7) 0.8 1 20 21 40 41 60 80 61 120 21 40 41 60 80 61 (1.25) 0.2 0.5 0.125 12.0 12.0 14.0 14.0 0.5 (1.0) 0.1 1.2max sanyo : tqfp80j(12x12)
LC87F76C8A no.a0858-7/24 system block diagram interrupt control standby control ir pla flash rom clock generator cf rc x?tal pc bus interface port 0 port 1 sio0 sio1 timer 0 (high speed clock counter) timer 1 timer 4 timer 5 timer 6 port 3 port 7 port 8 int0 to int3 noise rejection filter small signal detector acc b register c register psw rar ram stack pointer watchdog timer alu adc infrared remote control receiver timer 7 lcd controller vmrc uart1 on-chip debugger base timer day and time counter pwm/pwm5
LC87F76C8A no.a0858-8/24 pin description pin name i/o description option v ss 1 v ss 2 v ss 3 - - power supply pin no v dd 1 v dd 2 v dd 3 - + power supply pin no port0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? input for hold release ? input for port 0 interrupt ? shared pins p00: uart1 transmit * p01: uart1 receive * p05: clock output (system clock/subclock selectable) p06: timer 6 toggle output p07: timer 7 toggle output * when using uart, set p0lddr (poddr: bit0) to ?0? yes port1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1 pwml output p17: timer 1pwmh output/beeper output yes port3 p30 to p31 i/o ? 2-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p30: pwm4 output p31: pwm5 output yes port7 p70 to p73 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p70: int0 input/hold release input/timer 0l capture input/watchdog timer output p71: int1 input/hold release i nput/timer 0h capture input p72: int2 input/hold release input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (with noise filter)/timer 0 event input/timer 0h capture input/ infrared remote control receiver input ad converter input ports: an8 (p70), an9 (p71) ? interrupt acknowledge type rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable no continued on next page.
LC87F76C8A no.a0858-9/24 continued from preceding page. pin name i/o description option port8 p80 to p87 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? shared pins ad converter input ports: an0 to an7 small signal detector input port: micin (p87) no s0/pa0 to s7/pa7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pa) no s8/pb0 to s15/pb7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pb) no s16/pc0 to s23/pc7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pc) no s24/pd0 to s31/pd7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pd) no com0/pl0 to com3/pl3 i/o ? common output for lcd ? can be used as general-purpose input port (pl) no v1/pl4 to v3/pl6 i/o ? lcd drive bias power supply ? can be used as general-purpose input port (pl) ? shared pins on-chip debugger pins: dbgp0 (v1) to dbgp2 (v3) no res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? shared pins general-purpose input port must be connected to v dd 1 if not to be used. ad converter input port: an10 no xt2 i/o ? 32.768khz crystal oscillator output pin ? shared pins general-purpose i/o port must be set for oscillation and kept open if not to be used. ad converter input port: an11 no cf1 input ceramic resonator input pin no cf2 output ceramic resonator output pin no
LC87F76C8A no.a0858-10/24 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note) p00 to p07 each bit 2 n-channel open drain no 1 cmos programmable p10 to p17 each bit 2 n-channel open drain programmable 1 cmos programmable p30 to p31 each bit 2 n-channel open drain programmable p70 - no n-channel open drain programmable p71 to p73 - no cmos programmable p80 to p87 - no n-channel open drain no s0/pa0 to s31/pd7 - no cmos programmable com0/pl0 to com3/pl3 - no input only no v1/pl4 to v3/pl6 - no input only no xt1 - no input only no xt2 - no output for 32.768khz crystal oscillator (nch-open drain when in general-purpose output mode) no note: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). *1 connect the ic as shown below to minimize the noise input to the v dd 1 pin. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. *2 the internal memory is sustained by v dd 1. if none of v dd 2 and v dd 3 are backed up, the high level output at the ports are unstable in the hold backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. make sure that the port outputs are held at the low level in the hold backup mode. power supply lsi v dd 1 for backup *2 v dd 2 v dd 3 v ss 3 v ss 2 v ss 1
LC87F76C8A no.a0858-11/24 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1,v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 supply voltage for lcd vlcd v1/pl4, v2/pl5, v3/pl6 v dd 1=v dd 2=v dd 3 -0.3 v dd input voltage v i (1) ? port l ? xt1, cf1, res -0.3 v dd +0.3 input/output voltage v io (1) ? ports 0, 1, 3, 7, 8 ? ports a, b, c, d ? xt2 -0.3 v dd +0.3 v ioph(1) ports 0, 1 ? cm os output selected ? per applicable pin -10 ioph(2) port 3 ? cmos output selected ? per applicable pin -20 ioph(3) ports 71 to 73 per applicable pin -5 peak output current ioph(4) ports a, b, c, d per applicable pin -5 iomh(1) ports 0, 1 ? cm os output selected ? per applicable pin -7.5 iomh(2) port 3 ? cmos output selected ? per applicable pin -15 iomh(3) ports 71 to 73 per applicable pin -3 average output current (note 1-1) iomh(4) ports a, b, c, d per applicable pin -3 ioah(1) ports 0, 1, 31 total of currents at all applicable pins -25 ioah(2) port 30 total of currents at all applicable pins -15 ioah(3) ports 0, 1, 3 total of currents at all applicable pins -40 ioah(4) ports 71 to 73 total of currents at all applicable pins -5 ioah(5) ports a, b total of currents at all applicable pins -25 ioah(6) ports c, d total of currents at all applicable pins -25 high level output current total output current ioah(7) ports a, b, c, d total of currents at all applicable pins -45 iopl(1) ports 0, 1 per applicable pin 20 iopl(2) port 3 per applicable pin 30 iopl(3) ? ports 7, 8 ? xt2 per applicable pin 10 peak output current iopl(4) ports a, b, c, d per applicable pin 10 ioml(1) ports 0, 1 per applicable pin 15 ioml(2) port 3 per applicable pin 20 ioml(3) ? ports 7, 8 ? xt2 per applicable pin 7.5 low level output current average output current (note 1-1) ioml(4) ports a, b, c, d per applicable pin 7.5 ma note 1-1: average output current refers to the average of output currents measured for a period of 100ms. continued on next page.
LC87F76C8A no.a0858-12/24 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit ioal(1) ports 0, 1, 31 total of currents at all applicable pins 45 ioal(2) port 30 total of currents at all applicable pins 45 ioal(3) ports 0, 1, 3 total of currents at all applicable pins 80 ioal(4) ? ports 7, 8 ? xt2 total of currents at all applicable pins 20 ioal(5) ports a, b total of currents at all applicable pins 45 ioal(6) ports c, d total of currents at all applicable pins 45 low level output current total output current ioal(7) ports a, b, c, d total of currents at all applicable pins 80 ma qfp80(14 14) 290 maximum power dissipation pd max tqfp80j(12 12) ta=-20 to+70 c mw operating ambient temperature topr -20 +85 storage ambient temperature tstg -55 +125 c note 1-1: average output current refers to the average of output currents measured for a period of 100 ms. allowable operating range at ta = -20c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit v dd (1) 0-237 s tcyc 200 s 3.0 5.5 v dd (2) 0-356 s tcyc 200 s 2.5 5.5 operating supply voltage (note 2-1) v dd (3) v dd 1=v dd 2=v dd 3 0-712 s tcyc 200 s 2.2 5.5 memory sustaining supply voltage vhd v dd 1 ram and register contents sustained in hold mode 2.0 5.5 v ih (1) ? ports 0, 3, 8 ? ports a, b, c, d ? port l output disabled 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) ? port 1 ? ports 71 to 73 ? port 70 port input/ interrupt side ? output disabled ? when int1vtsl=0 (p71only) 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) port 71 interrupt side ? output disabled ? when int1vtsl=1 2.2 to 5.5 0.85v dd v dd v ih (4) port 87 small signal input side output disabled 2.2 to 5.5 0.75v dd v dd v ih (5) port 70 watchdog timer side output disabled 2.2 to 5.5 0.9v dd v dd high level input voltage v ih (6) xt1, xt2, cf1, res 2.2 to 5.5 0.75v dd v dd v note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. continued on next page.
LC87F76C8A no.a0858-13/24 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 4.0 to 5.5 v ss 0.15v dd +0.4 v il (1) ? ports 0, 3, 8 ? ports a, b, c, d ? port l output disabled 2.2 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.1v dd +0.4 vil( 2) ? port 1 ? ports 71 to 73 ? port 70 port input/ interrupt side ? output disabled ? when int1vtsl=0 (p71 only) 2.2 to 4.0 v ss 0.2v dd v il (3) port 71 interrupt side ? output disabled ? when int1vtsl=1 2.2 to 5.5 v ss 0.45v dd v il (4) port 87 small signal input side output disabled 2.2 to 5.5 v ss 0.25v dd v il (5) port 70 watchdog timer side output disabled 2.2 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (6) xt1, xt2, cf1, res 2.2 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.237 200 2.5 to 5.5 0.356 200 instruction cycle time (note 2-2) tcyc 2.2 to 5.5 0.712 200 s 3.0 to 5.5 0.1 12 2.5 to 5.5 0.1 8 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty505% 2.2 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 2.5 to 5.5 0.2 16 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/2 2.2 to 5.5 0.2 8 fmcf(1) cf1, cf2 ? 12mhz ceramic oscillation ? see figure 1. 3.0 to 5.5 12 fmcf(2) cf1, cf2 ? 8mhz ceramic oscillation ? see figure 1. 2.5 to 5.5 8 fmcf(3) cf1, cf2 ? 4mhz ceramic oscillation ? see figure 1. 2.2 to 5.5 4 fmrc internal rc oscillation 2.2 to 5.5 0.3 1.0 2.0 fmvmrc(1) ? multifrequency rc source oscillation ? vmraj2 to 0=4, vmfaj2 to 0=0, when vmsl4m=0 2.2 to 5.5 10 fmvmrc(2) ? multifrequency rc source oscillation ? vmraj2 to 0=4, vmfaj2 to 0=0, when vmsl4m=1 2.2 to 5.5 4 mhz oscillation frequency range (note 2-3) fsx?tal xt1, xt2 ? 32.768khz crystal oscillation ? see figure 2. 2.2 to 5.5 32.768 khz opvmrc(1) when vmsl4m=0 2.2 to 5.5 8 10 12 multifrequency rc oscillation usable range opvmrc(2) when vmsl4m=1 2.2 to 5.5 3.5 4 4.5 mhz vmadj(1) vmrajn 1step (wide range) 2.2 to 5.5 8 24 64 multifrequency rc oscillation adjustment range vmadj(2) vmfajn 1step (narrow range) 2.2 to 5.5 1 4 8 % note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants.
LC87F76C8A no.a0858-14/24 electrical characteristics at ta = -20c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ? ports 0, 1, 3, 7, 8 ? ports a, b, c, d ? port l ? output disabled ? pull-up resistor off ? v in =v dd (including output tr's off leakage current) 2.2 to 5.5 1 i ih (2) res v in =v dd 2.2 to 5.5 1 i ih (3) xt1, xt2 ? when configured as input ports ? v in =v dd 2.2 to 5.5 1 i ih (4) cf1 v in =v dd 2.2 to 5.5 15 4.5 to 5.5 4.2 8.5 15 high level input current i ih (5) port 87 small signal input side v in =vbis+0.5v (vbis denotes bias voltage) 2.2 to 4.5 1.5 5.5 10 i il (1) ? ports 0, 1, 3, 7, 8 ? ports a, b, c, d ? port l ? output disabled ? pull-up resistor off ? v in =v ss (including output tr's off leakage current) 2.2 to 5.5 -1 i il (2) res v in =v ss 2.2 to 5.5 -1 i il (3) xt1, xt2 ? when configured as input ports ? v in =v ss 2.2 to 5.5 -1 iil(4) cf1 v in =v ss 2.2 to 5.5 -15 4.5 to 5.5 -15 -8.5 -4.2 low level input current i il (5) port 87 small signal input side v in =vbis-0.5v (vbis denotes bias voltage) 2.2 to 4.5 -10 -5.5 -1.5 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) cmos output ports 0, 1 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (4) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (6) cmos output ports 30, 31 i oh =-1ma 2.2 to 5-5 v dd -0.4 v oh (7) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (8) ports 71 to 73 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (9) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (10) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (11) ports a, b, c, d i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ports 0, 1 ? port 3 (pwm4, 5 function output mode) i ol =1ma 2.2 to 5.5 0.4 v ol (4) i ol =30ma 4.5 to 5.5 1.5 v ol (5) i ol =5ma 3.0 to 5.5 0.4 v ol (6) port 3 (port function output mode) i ol =2.5ma 2.2 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 v ol (8) ? ports 7, 8 ? xt2 i ol =1ma 2.2 to 5.5 0.4 v ol (9) i oh =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (10) ports a, b, c, d i ol =1ma 2.2 to 5.5 0.4 vodls s0 to s31 ? i o =0ma ? vlcd, 2/3vlcd 1/3vlcd level output ? see fig. 8. 2.2 to 5.5 0 0.2 lcd output voltage deviation vodlc com0 to com3 ? i o =0ma ? vlcd, 2/3vlcd 1/2vlcd, 1/3vlcd level output ? see fig. 8. 2.2 to 5.5 0 0.2 v rlcd(1) resistance per one bias resister see fig. 8. 2.2 to 5.5 60 lcd bias resistor rlcd(2) ? resistance per one bias resister ? 1/2 resistance mode see fig. 8. 2.2 to 5.5 30 k continued on next page.
LC87F76C8A no.a0858-15/24 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit rpu(1) 4.5 to 5.5 15 35 80 pull-up mos tr. resistance rpu(2) ? ports 0, 1, 3, 7 ? ports a, b, c, d v oh =0-9v dd 2.2 to 4.5 18 50 150 k vhys(1) ? ports 1, 7 ? res 2.2 to 5.5 0.1v dd hysteresis voltage vhys(2) port 87 small signal input side 2.2 to 5.5 0.1v dd v pin capacitance cp all pins ? v in =v ss for pins other than that under test ? f=1mhz ? ta=25 c 2.2 to 5.5 10 pf input sensitivity vsen port 87 small signal input side 2.2 to 5.5 0.12v dd vp-p serial i/o characteristics at ta = -20c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 2.2 to 5.5 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. 2.2 to 5.5 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 tddo(1) ? continuous data transmission/reception mode ? (note 4-1-3) ( 1/3)tcyc +0.05 input clock tddo(2) ? synchronous 8-bit mode ? (note 4-1-3) 1tcyc +0.05 serial output output clock output delay time tddo(3) so0(p10), sb0(p11) (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous transmission/reception m ode, a time from si0run being set when serial clock is "h" to the first falling edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
LC87F76C8A no.a0858-16/24 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig.6. 2.2 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.2 to 5.5 1/2 tsck data setup time tsdi(2) 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.2 to 5.5 0.03 serial output output delay time tddo(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -20c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 256 tpih(5) tpil(5) micin(p87) the pulses can be counted by the small signal sensor/counter. 2.2 to 5.5 1 tcyc tpih(6) tpil(6) rmin(p73) the pulses can be recognized as signals by the infrared remote control receiver circuit. 2.2 to 5.5 3 rmck (note5-1) high/low level pulse width tpil(7) res resetting is enabled. 2.2 to 5.5 2000 s note 5-1: rmck denotes the frequency of the base clock (1tcyc to 128tcyc/subclock source oscillation frequency) for the infrared remote control receiver circuit
LC87F76C8A no.a0858-17/24 ad converter characteristics at v ss 1 = v ss 2 = 0v <12bits ad converter mode at ta =-30 to +70 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb 4.0 to 5.5 32 100 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 40 100 s analog input voltage range vain v ss v dd v iainh vain=v dd 1 analog port input current iainl an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2) vain=v ss 5 -1 a <8bits ad converter mode at ta =-30 to +70 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.0 to 5.5 20 90 see "conversion time calculation method." (note 6-2) 3.0 to 5.5 40 90 conversion time tcad see "conversion time calculation method." (note 6-2) ta=-10 to 50 c 3.0 to 5.5 v ss v dd s analog input voltage range vain 3.0 to 5.5 1 v iainh vain=v dd 3.0 to 5.5 -1 analog port input current iainl an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1) an11(xt2) vain=v ss 3.0 to 5.5 -1 a 12bits ad converter mode: tcad (conversion ti me) = ((52/(division ratio)) + 2) (1/3)tcyc 8bits ad converter mode: tcad (conversion time) = ((32/(division ratio)) + 2) (1/3)tcyc conversion time (tcad)[ s] external oscillator fmcf[mhz] supply voltage range v dd [v] system clock division (sysdiv) cycle time tcyc [ns] ad frequency division ratio (addiv) 12-bit ad 8-bit ad 4.0 to 5.5 1/1 250 1/8 34.8 21.5 12 3.0 to 5.5 1/1 250 1/16 69.5 42.8 note 6-1: the quantization er ror (1/2lsb) is excluded fro m the absolute accuracy value. the absolute accuracy refers to the accuracy that is measured while there is no change in the i/o state of the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued till the time the complete digital- conversion-value corresponding to the analog input value is loaded in the required register.
LC87F76C8A no.a0858-18/24 consumption current characteristics at ta = -20c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/rema rks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 8.2 18.0 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/1 frequency division ratio 3.0 to 3.6 4.8 10.6 iddop(3) 4.5 to 5.5 6.4 13.9 iddop(4) 3.0 to 3.6 3.8 8.8 iddop(5) ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/1 frequency division ratio 2.5 to 3.0 3.0 6.7 iddop(6) 4.5 to 5.5 3.9 8.5 iddop(7) 3.0 to 3.6 2.5 5.2 iddop(8) ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/2 frequency division ratio 2.2 to 3.0 2.1 4.3 iddop(9) 4.5 to 5.5 0.7 1.6 iddop(10) 3.0 to 3.6 0.4 0.9 iddop(11) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to internal rc oscillation ? multifrequency rc oscillation stopped ? 1/2 frequency division ratio 2.2 to 3.0 0.3 0.7 iddop(12) 4.5 to 5.5 7.6 16.7 iddop(13) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped ? system clock set to 10mhz multifrequency rc oscillation ? 1/1 frequency division ratio 3.0 to 3.6 4.3 9.5 iddop(14) 4.5 to 5.5 4.1 8.9 iddop(15) 3.0 to 3.6 2.3 5.0 iddop(16) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped ? system clock set to 4mhz multifrequency rc oscillation ? 1/1 frequency division ratio 2.2 to 3.0 2.0 4.1 ma iddop(17) 4.5 to 5.5 41.8 171.4 iddop(18) 3.0 to 3.6 17.7 84.3 normal mode consumption current (note 7-1) iddop(19) v dd 1 =v dd 2 =v dd 3 ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/2 frequency division ratio 2.2 to 3.0 13 67.2 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
LC87F76C8A no.a0858-19/24 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(1) 4.5 to 5.5 3.7 8.2 iddhalt(2) halt mode ? fmcf=12mhz ceramic oscillation ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 12mhz side. ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/1 frequency division ratio 3.0 to 3.6 1.9 4.3 iddhalt(3) 4.5 to 5.5 6.4 13.9 iddhalt(4) 3.0 to 3.6 3.8 8.8 iddhalt(5) halt mode ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/1 frequency division ratio 2.5 to 3.0 3.0 6.7 iddhalt(6) 4.5 to 5.5 3.9 8.5 iddhalt(7) 3.0 to 3.6 2.5 5.2 iddhalt(8) halt mode ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/2 frequency division ratio 2.2 to 3.0 2.1 4.3 iddhalt(9) 4.5 to 5.5 0.4 0.9 iddhalt(10) 3.0 to 3.6 0.18 0.4 iddhalt(11) halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to internal rc oscillation ? multifrequency rc oscillation stopped ? 1/2 frequency division ratio 2.2 to 3.0 0.13 0.3 iddhalt(12) 4.5 to 5.5 3.4 7.3 iddhalt(13) halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped ? system clock set to 10mhz multifrequency rc oscillation ? 1/1 frequency division ratio 3.0 to 3.6 1.7 3.7 iddhalt(14) 4.5 to 5.5 1.7 3.9 iddhalt(15) 3.0 to 3.6 0.8 1.8 iddhalt(16) halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped ? system clock set to 4mhz multifrequency rc oscillation ? 1/1 frequency division ratio 2.2 to 3.0 0.6 1.4 ma iddhalt(17) 4.5 to 5.5 25.7 141.9 iddhalt(18) 3.0 to 3.6 8.3 66.6 halt mode consumption current (note 7-1) iddhalt(19) v dd 1 =v dd 2 =v dd 3 halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? multifrequency rc oscillation stopped ? 1/2 frequency division ratio 2.2 to 3.0 5.2 52.3 iddhold(1) 4.5 to 5.5 0.14 28.0 iddhold(2) 3.0 to 3.6 0.03 19.0 hold mode consumption current iddhold(3) v dd 1 hold mode ? cf1=v dd or open (external clock mode) 2.2 to 3.0 0.03 16.0 iddhold(4) 4.5 to 5.5 21.9 80 iddhold(5) 3.0 to 3.6 6.3 37 clock hold mode consumption current iddhold(6) v dd 1 clock hold mode ? cf1=v dd or open (external clock mode) ? fmx?tal=32.768khz cr ystal oscillation mode 2.2 to 3.0 3.6 30 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors.
LC87F76C8A no.a0858-20/24 f-rom programming characteristics at ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? 128-byte programming ? erasing current included 3.0 to 5.5 ma programming time tfw(1) ? 128-byte programming ? erasing current included ? time for setting up 128-byte data is excluded. 3.0 to 5.5 ms uart (full duplex) op erating conditions at ta = -20 to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit transfer rate ubr utx(p00), urx(p01) 2.2 to 5.5 16/3 8192/3 tcyc data length: 7/8/9 bits (lsb first) stop bits: 1 bit (2-bit in continuous data transmission mode) parity bits: none example of 8-bit data transmission mode processing (transmit data=55h) example of 8-bit data reception m ode processing (r eceive data=55h) *when using uart, set p0lddr (poddr: bit0) to ?0? transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit ubr receive data (lsb first) start of reception end of reception start bit stop bit
LC87F76C8A no.a0858-21/24 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0g52-r0 (10) (10) open 2.2k 2.8 to 5.5 built-in c1, c2 cstce8m00g52-r0 (10) (10) open 1.0k 8mhz murata cstls8m00g52-r0 (15) (15) open 1.0k 2.5 to 5.5 built-in c1, c2 cstcr4m00f53-r0 (15) (15) open 2.2k 4mhz murata cstls4m0053-b0 (15) (15) open 2.2k 2.1 to 5.5 built-in c1, c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). caution: the components that are involved in oscillation shoul d be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 c1 rd1 c2 cf rf1
LC87F76C8A no.a0858-22/24 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization times operating v dd lower limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal hold release signal valid tmscf tmsx?tal hold halt hold reset signal absent
LC87F76C8A no.a0858-23/24 figure 5 reset circuit figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic's operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
LC87F76C8A no.a0858-24/24 figure 8 lcd bias resistors ps vlcd sw: on when vlcd=v dd 2/3vlcd 1/2vlcd 1/3vlcd sw : on/off (programmable) v dd gnd rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d this catalog provides information as of august, 2006. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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